ARCHITECTURE PROPOSAL OF ANALOG INTERVAL TYPE-2 FUZZY LOGIC INFERENCE SYSTEMS

Abstract

This paper proposes an architecture for analog implementation of a Type-2 Fuzzy Inference Circuit, which is the main block of the Interval Type-2 Fuzzy Logic Controller (IT2FLC) chip. This architecture is composed of Minimum (Min) and Maximum (Max) circuits. The former are used to combine the antecedents of the rules and the later are used to combine the consequents currents of the rule (from the type-2 fuzzifier circuit). These circuits operate in current mode, with a supply voltage of 3.3V. The proposed architecture (which consists of two inputs with two membership functions for each one, four rules, and one output with three membership functions) was validated through Mentor Graphics simulation in a 0.35µm CMOS technology. The Mentor simulation result of the proposed architecture was compared with similar a Type-2 Fuzzy Inference System simulated in Interval Type-2 Fuzzy Logic Toolbox from Matlab.